dOSEK/llvm.git
5 years agoUpdate Release Notes master release_34
Tom Stellard [Fri, 16 May 2014 21:12:49 +0000 (21:12 +0000)]
Update Release Notes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@209031 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r208908:
Tom Stellard [Thu, 15 May 2014 20:56:00 +0000 (20:56 +0000)]
Merging r208908:

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r208908 | thomas.stellard | 2014-05-15 15:50:25 -0400 (Thu, 15 May 2014) | 7 lines

autoconf: Fix libLLVM-Major-Minor-Patch.so symlink

The symlink needs to point to a relative path, so we don't break
building in a chroot.

Tested-by: Laurent Carlier <lordheavym@gmail.org>
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5 years agoMerging r208501:
Tom Stellard [Thu, 15 May 2014 20:55:58 +0000 (20:55 +0000)]
Merging r208501:

------------------------------------------------------------------------
r208501 | hfinkel | 2014-05-11 12:23:29 -0400 (Sun, 11 May 2014) | 9 lines

[PowerPC] On PPC32, 128-bit shifts might be runtime calls

The counter-loops formation pass needs to know what operations might be
function calls (because they can't appear in counter-based loops). On PPC32,
128-bit shifts might be runtime calls (even though you can't use __int128 on
PPC32, it seems that SROA might form them).

Fixes PR19709.

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5 years agoMerging r208721:
Tom Stellard [Thu, 15 May 2014 00:15:27 +0000 (00:15 +0000)]
Merging r208721:

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r208721 | thomas.stellard | 2014-05-13 15:37:03 -0400 (Tue, 13 May 2014) | 11 lines

autoconf: Fix soname for libLLVM-Major.Minor.so (2nd try)

We were using libLLVM-Major.Minor.Patch.so for the soname, but we
need the soname to stay consistent for all Major.Minor.* releases
otherwise operating system distributors  will need to rebuild all
packages that link with LLVM every time there is a new point release.

This patch also reverses the compatibility symlink, so
libLLVM-Major.Minor.Patch.so is now a symlink that points
to libLLVM-Major-Minor.so.

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5 years agoMerging r207990:
Tom Stellard [Thu, 15 May 2014 00:15:24 +0000 (00:15 +0000)]
Merging r207990:

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r207990 | marek.olsak | 2014-05-05 15:30:54 -0400 (Mon, 05 May 2014) | 6 lines

R600/SI: allow 5 more input SGPRs to a shader

Our OpenGL driver needs 22 SGPRs (16 user SGPRs + 6 streamout non-user SGPRs).

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
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5 years agoBump version to 3.4.2
Tom Stellard [Mon, 12 May 2014 17:11:16 +0000 (17:11 +0000)]
Bump version to 3.4.2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@208597 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoUpdate Release Notes for 3.4.1
Tom Stellard [Mon, 12 May 2014 17:11:15 +0000 (17:11 +0000)]
Update Release Notes for 3.4.1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@208596 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r203581:
Tom Stellard [Fri, 11 Apr 2014 21:04:44 +0000 (21:04 +0000)]
Merging  r203581:

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r203581 | hans | 2014-03-11 11:49:24 -0400 (Tue, 11 Mar 2014) | 7 lines

X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)

This fixes the bug where we would bitcast the 64-bit floating point result
of cmpneqsd to a 64-bit integer even on 32-bit targets.

Differential Revision: http://llvm-reviews.chandlerc.com/D3009

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5 years agoMerging r198937:
Tom Stellard [Fri, 11 Apr 2014 20:23:49 +0000 (20:23 +0000)]
Merging r198937:

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r198937 | kristof.beyls | 2014-01-10 08:41:49 -0500 (Fri, 10 Jan 2014) | 2 lines

Make sure -use-init-array has intended effect on all AArch64 ELF targets, not just linux.

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5 years agoMerging r202774:
Tom Stellard [Fri, 11 Apr 2014 19:55:07 +0000 (19:55 +0000)]
Merging r202774:

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r202774 | reid | 2014-03-03 19:33:17 -0500 (Mon, 03 Mar 2014) | 7 lines

MC: Fix Intel assembly parser for [global + offset]

We were dropping the displacement on the floor if we also had some
immediate offset.

Should fix PR19033.

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5 years agoMerging r201126:
Tom Stellard [Fri, 11 Apr 2014 19:35:47 +0000 (19:35 +0000)]
Merging r201126:

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r201126 | craig.topper | 2014-02-10 23:05:33 -0500 (Mon, 10 Feb 2014) | 2 lines

Changed attributes of all gather intrinsics from IntrReadMem to IntrReadArgMem as they access only memory based on argument. Patch by Robert Khasanov.

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5 years agoMerging r201507:
Tom Stellard [Fri, 11 Apr 2014 19:35:46 +0000 (19:35 +0000)]
Merging r201507:

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r201507 | craig.topper | 2014-02-17 05:03:43 -0500 (Mon, 17 Feb 2014) | 2 lines

Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860.

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5 years agoMerging r205067:
Tom Stellard [Fri, 11 Apr 2014 19:35:44 +0000 (19:35 +0000)]
Merging r205067:

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r205067 | ahatanaka | 2014-03-28 19:28:07 -0400 (Fri, 28 Mar 2014) | 7 lines

[x86] Fix printing of register operands with q modifier.

Emit 32-bit register names instead of 64-bit register names if the target does
not have 64-bit general purpose registers.

<rdar://problem/14653996>

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5 years agoMerging r200028:
Tom Stellard [Fri, 11 Apr 2014 19:35:42 +0000 (19:35 +0000)]
Merging r200028:

------------------------------------------------------------------------
r200028 | benny.kra | 2014-01-24 14:02:37 -0500 (Fri, 24 Jan 2014) | 4 lines

InstCombine: Don't try to use aggregate elements of ConstantExprs.

PR18600.

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5 years agoMerging r199351:
Tom Stellard [Fri, 11 Apr 2014 19:35:41 +0000 (19:35 +0000)]
Merging r199351:

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r199351 | aschwaighofer | 2014-01-15 23:53:18 -0500 (Wed, 15 Jan 2014) | 5 lines

BasicAA: We need to check both access sizes when comparing a gep and an
underlying object of unknown size.

Fixes PR18460.

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5 years agoMerging r198400:
Tom Stellard [Fri, 11 Apr 2014 19:35:39 +0000 (19:35 +0000)]
Merging r198400:

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r198400 | aschwaighofer | 2014-01-03 00:47:03 -0500 (Fri, 03 Jan 2014) | 18 lines

BasicAA: Use reachabilty instead of dominance for checking value equality in phi
cycles

This allows the value equality check to work even if we don't have a dominator
tree. Also add some more comments.

I was worried about compile time impacts and did not implement reachability but
used the dominance check in the initial patch. The trade-off was that the
dominator tree was required.
The llvm utility function isPotentiallyReachable cuts off the recursive search
after 32 visits. Testing did not show any compile time regressions showing my
worries unjustfied.

No compile time or performance regressions at O3 -flto -mavx on test-suite +
externals.

Addresses review comments from r198290.

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5 years agoMerging r198290:
Tom Stellard [Fri, 11 Apr 2014 19:35:37 +0000 (19:35 +0000)]
Merging r198290:

------------------------------------------------------------------------
r198290 | aschwaighofer | 2014-01-01 22:31:36 -0500 (Wed, 01 Jan 2014) | 23 lines

BasicAA: Fix value equality and phi cycles

When there are cycles in the value graph we have to be careful interpreting
"Value*" identity as "value" equivalence. We interpret the value of a phi node
as the value of its operands.
When we check for value equivalence now we make sure that the "Value*" dominates
all cycles (phis).

%0 = phi [%noaliasval, %addr2]
%l = load %ptr
%addr1 = gep @a, 0, %l
%addr2 = gep @a, 0, (%l + 1)
store %ptr ...

Before this patch we would return NoAlias for (%0, %addr1) which is wrong
because the value of the load is from different iterations of the loop.

Tested on x86_64 -mavx at O3 and O3 -flto with no performance or compile time
regressions.

PR18068
radar://15653794

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5 years agoMerging r196970:
Tom Stellard [Fri, 11 Apr 2014 19:35:34 +0000 (19:35 +0000)]
Merging r196970:

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r196970 | fang | 2013-12-10 16:37:41 -0500 (Tue, 10 Dec 2013) | 3 lines

on darwin<10, fallback to .weak_definition (PPC,X86)
.weak_def_can_be_hidden was not yet supported by the system assembler

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5 years agoMerging r195971:
Tom Stellard [Fri, 11 Apr 2014 19:26:56 +0000 (19:26 +0000)]
Merging r195971:

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r195971 | juergen | 2013-11-29 22:07:16 -0500 (Fri, 29 Nov 2013) | 2 lines

Force CPU type to unbreak unit tests on Haswell machines.

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5 years agoMerging r200705:
Tom Stellard [Wed, 9 Apr 2014 15:50:15 +0000 (15:50 +0000)]
Merging r200705:

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r200705 | hfinkel | 2014-02-03 12:27:25 -0500 (Mon, 03 Feb 2014) | 5 lines

Expand vector bswap in LegalizeVectorOps

ISD::BSWAP was missing from the list of node types that should be expanded
element-wise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205910 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r205630:
Tom Stellard [Wed, 9 Apr 2014 15:40:10 +0000 (15:40 +0000)]
Merging r205630:

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r205630 | hfinkel | 2014-04-04 11:15:57 -0400 (Fri, 04 Apr 2014) | 6 lines

[PowerPC] Add a full condition code register to make the "cc" clobber work

gcc inline asm supports specifying "cc" as a clobber of all condition
registers. Add just enough modeling of the full register to make this work.
Fixed PR19326.

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5 years agoMerging r204304:
Tom Stellard [Wed, 9 Apr 2014 15:24:22 +0000 (15:24 +0000)]
Merging r204304:

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r204304 | Hao.Liu | 2014-03-20 01:36:59 -0400 (Thu, 20 Mar 2014) | 2 lines

[ARM]Fix an assertion failure in A15SDOptimizer about DPair reg class by treating DPair as QPR.

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5 years agoMerging r201841:
Tom Stellard [Wed, 9 Apr 2014 15:24:19 +0000 (15:24 +0000)]
Merging r201841:

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r201841 | Kevin.Qin | 2014-02-21 02:45:48 -0500 (Fri, 21 Feb 2014) | 2 lines

[AArch64] Add register constraints to avoid generating STLXR and STXR with unpredictable behavior.

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5 years agoMerging r201541:
Tom Stellard [Wed, 9 Apr 2014 15:24:16 +0000 (15:24 +0000)]
Merging r201541:

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r201541 | jiangning.liu | 2014-02-17 21:37:42 -0500 (Mon, 17 Feb 2014) | 2 lines

Fix a typo about lowering AArch64 va_copy.

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5 years agoMerging r199369:
Tom Stellard [Wed, 9 Apr 2014 15:24:12 +0000 (15:24 +0000)]
Merging r199369:

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r199369 | jiangning.liu | 2014-01-16 04:16:13 -0500 (Thu, 16 Jan 2014) | 2 lines

For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback.

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5 years agoMerging r204155:
Tom Stellard [Wed, 9 Apr 2014 00:20:58 +0000 (00:20 +0000)]
Merging r204155:

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r204155 | wschmidt | 2014-03-18 10:32:50 -0400 (Tue, 18 Mar 2014) | 16 lines

Fix PR19144: Incorrect offset generated for int-to-fp conversion at -O0.

When converting a signed 32-bit integer to double-precision floating point on
hardware without a lfiwax instruction, we have to instead use a lfd followed
by fcfid.  We were erroneously offsetting the address by 4 bytes in
preparation for either a lfiwax or lfiwzx when generating the lfd.  This fixes
that silly error.

This was not caught in the test suite since the conversion tests were run with
-mcpu=pwr7, which implies availability of lfiwax.  I've added another test
case for older hardware that checks the code we expect in the absence of
lfiwax and other flavors of fcfid.  There are fewer tests in this test case
because we punt to DAG selection in more cases on older hardware.  (We must
generate complex fiddly sequences in those cases, and there is marginal
benefit in duplicating that logic in fast-isel.)

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5 years agoMerging r203054:
Tom Stellard [Wed, 9 Apr 2014 00:20:55 +0000 (00:20 +0000)]
Merging r203054:

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r203054 | hfinkel | 2014-03-05 20:28:23 -0500 (Wed, 05 Mar 2014) | 7 lines

The PPC global base register cannot be r0

The global base register cannot be r0 because it might end up as the first
argument to addi or addis. Fixes PR18316.

I don't have a small stable test case.

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5 years agoMerging r202192:
Tom Stellard [Wed, 9 Apr 2014 00:20:52 +0000 (00:20 +0000)]
Merging r202192:

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r202192 | hfinkel | 2014-02-25 15:51:50 -0500 (Tue, 25 Feb 2014) | 5 lines

Account for 128-bit integer operations in PPCCTRLoops

We need to abort the formation of counter-register-based loops where there are
128-bit integer operations that might become function calls.

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5 years agoMerging r200288:
Tom Stellard [Wed, 9 Apr 2014 00:20:48 +0000 (00:20 +0000)]
Merging r200288:

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r200288 | hfinkel | 2014-01-28 00:32:58 -0500 (Tue, 28 Jan 2014) | 5 lines

Handle spilling the PPC GPRC_NOR0 register class

GPRC_NOR0 is not a subclass of GPRC (because it also contains the ZERO pseudo
register). As a result, we also need to check for it in the spilling code.

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5 years agoMerging r199832:
Tom Stellard [Wed, 9 Apr 2014 00:20:45 +0000 (00:20 +0000)]
Merging r199832:

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r199832 | rafael.espindola | 2014-01-22 15:20:52 -0500 (Wed, 22 Jan 2014) | 11 lines

Fix pr18515.

My understanding (from reading just the llvm code) is that
* most ppc cpus have a "sync n" instruction and an msync alias that is
* "sync 0".
* "book e" cpus instead have a msync instruction and not the more
general "sync n"

This patch reflects that in the .td files, allowing a single codepath
for
asm ond obj streamer and incidentelly fixes a crash when EmitRawText was
called on a obj streamer.

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5 years agoMerging r199763:
Tom Stellard [Wed, 9 Apr 2014 00:20:42 +0000 (00:20 +0000)]
Merging r199763:

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r199763 | hfinkel | 2014-01-21 15:15:58 -0500 (Tue, 21 Jan 2014) | 9 lines

Fix pointer info on PPC byval stores

For PPC64 SVR (and Darwin), the stores that take byval aggregate parameters
from registers into the stack frame had MachinePointerInfo objects with
incorrect offsets. These offsets are relative to the object itself, not to the
stack frame base.

This fixes self hosting on PPC64 when compiling with -enable-aa-sched-mi.

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5 years agoMerging r199570:
Tom Stellard [Wed, 9 Apr 2014 00:20:38 +0000 (00:20 +0000)]
Merging r199570:

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r199570 | aschwaighofer | 2014-01-18 22:18:31 -0500 (Sat, 18 Jan 2014) | 11 lines

LoopVectorizer: A reduction that has multiple uses of the reduction value is not
a reduction.

Really. Under certain circumstances (the use list of an instruction has to be
set up right - hence the extra pass in the test case) we would not recognize
when a value in a potential reduction cycle was used multiple times by the
reduction cycle.

Fixes PR18526.
radar://15851149

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5 years agoMerging r198425:
Tom Stellard [Wed, 9 Apr 2014 00:20:34 +0000 (00:20 +0000)]
Merging r198425:

------------------------------------------------------------------------
r198425 | dpeixott | 2014-01-03 12:20:01 -0500 (Fri, 03 Jan 2014) | 33 lines

Fix loop rerolling pass failure with non-consant loop lower bound

The loop rerolling pass was failing with an assertion failure from a
failed cast on loops like this:

  void foo(int *A, int *B, int m, int n) {
    for (int i = m; i < n; i+=4) {
      A[i+0] = B[i+0] * 4;
      A[i+1] = B[i+1] * 4;
      A[i+2] = B[i+2] * 4;
      A[i+3] = B[i+3] * 4;
    }
  }

The code was casting the SCEV-expanded code for the new
induction variable to a phi-node. When the loop had a non-constant
lower bound, the SCEV expander would end the code expansion with an
add insted of a phi node and the cast would fail.

It looks like the cast to a phi node was only needed to get the
induction variable value coming from the backedge to compute the end
of loop condition. This patch changes the loop reroller to compare
the induction variable to the number of times the backedge is taken
instead of the iteration count of the loop. In other words, we stop
the loop when the current value of the induction variable ==
IterationCount-1. Previously, the comparison was comparing the
induction variable value from the next iteration == IterationCount.

This problem only seems to occur on 32-bit targets. For some reason,
the loop is not rerolled on 64-bit targets.

PR18290

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5 years agoMerging r203146:
Tom Stellard [Tue, 8 Apr 2014 23:00:32 +0000 (23:00 +0000)]
Merging r203146:

------------------------------------------------------------------------
r203146 | reid | 2014-03-06 14:19:12 -0500 (Thu, 06 Mar 2014) | 6 lines

MS asm: The initial dot in struct access is optional

Fixes PR18994.

Tests, once again, in that other repository.  =P

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5 years agoMerging r205738:
Tom Stellard [Tue, 8 Apr 2014 21:47:17 +0000 (21:47 +0000)]
Merging r205738:

------------------------------------------------------------------------
r205738 | atrick | 2014-04-07 17:29:22 -0400 (Mon, 07 Apr 2014) | 16 lines

Put a limit on ScheduleDAGSDNodes::ClusterNeighboringLoads to avoid blowing up compile time.

Fixes PR16365 - Extremely slow compilation in -O1 and -O2.

The SD scheduler has a quadratic implementation of load clustering
which absolutely blows up compile time for large blocks with constant
pool loads. The MI scheduler has a better implementation of load
clustering. However, we have not done the work yet to completely
eliminate the SD scheduler. Some benchmarks still seem to benefit from
early load clustering, although maybe by chance.

As an intermediate term fix, I just put a nice limit on the number of
DAG users to search before finding a match. With this limit there are no
binary differences in the LLVM test suite, and the PR16365 test case
does not suffer any compile time impact from this routine.

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5 years agoMerging r200202:
Tom Stellard [Tue, 8 Apr 2014 21:47:15 +0000 (21:47 +0000)]
Merging r200202:

------------------------------------------------------------------------
r200202 | stpworld | 2014-01-27 04:43:10 -0500 (Mon, 27 Jan 2014) | 2 lines

Additional fix for 200201: due to dependence on bitwidth test was moved to X86 directory.

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5 years agoMerging r200201:
Tom Stellard [Tue, 8 Apr 2014 21:47:12 +0000 (21:47 +0000)]
Merging r200201:

------------------------------------------------------------------------
r200201 | stpworld | 2014-01-27 04:18:31 -0500 (Mon, 27 Jan 2014) | 31 lines

Fix for PR18102.

Issue outcomes from DAGCombiner::MergeConsequtiveStores, more precisely from
mem-ops sequence sorting.

Consider, how MergeConsequtiveStores works for next example:

store i8 1, a[0]
store i8 2, a[1]
store i8 3, a[1]   ; a[1] again.
return   ; DAG starts here

1. Method will collect all the 3 stores.
2. It sorts them by distance from the base pointer (farthest with highest
index).
3. It takes first consecutive non-overlapping stores and (if possible) replaces
them with a single store instruction.

The point is, we can't determine here which 'store' instruction
would be the second after sorting ('store 2' or 'store 3').
It happens that 'store 3' would be the second, and 'store 2' would be the third.

So after merging we have the next result:

store i16 (1 | 3 << 8), base   ; is a[0] but bit-casted to i16
store i8 2, a[1]

So actually we swapped 'store 3' and 'store 2' and got wrong contents in a[1].

Fix: In sort routine just also take into account mem-op sequence number.

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5 years agoMerging r203725:
Tom Stellard [Tue, 8 Apr 2014 21:18:20 +0000 (21:18 +0000)]
Merging r203725:

------------------------------------------------------------------------
r203725 | rafael.espindola | 2014-03-12 18:03:43 -0400 (Wed, 12 Mar 2014) | 2 lines

This test need the X86 backend, move it to the X86 sub directory.

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5 years agoMerging r203719:
Tom Stellard [Tue, 8 Apr 2014 21:18:17 +0000 (21:18 +0000)]
Merging r203719:

------------------------------------------------------------------------
r203719 | mzolotukhin | 2014-03-12 17:31:05 -0400 (Wed, 12 Mar 2014) | 4 lines

PR17473:
Don't normalize an expression during postinc transformation unless it's
invertible.

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5 years agoMerging r202273:
Tom Stellard [Tue, 8 Apr 2014 21:18:14 +0000 (21:18 +0000)]
Merging r202273:

------------------------------------------------------------------------
r202273 | atrick | 2014-02-26 11:31:56 -0500 (Wed, 26 Feb 2014) | 4 lines

Fix PR18165: LSR must avoid scaling factors that exceed the limit on truncated use.

Patch by Michael Zolotukhin!

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5 years agoMerging r201104:
Tom Stellard [Tue, 8 Apr 2014 21:18:11 +0000 (21:18 +0000)]
Merging r201104:

------------------------------------------------------------------------
r201104 | chandlerc | 2014-02-10 14:39:35 -0500 (Mon, 10 Feb 2014) | 26 lines

[LPM] A terribly simple fix to a terribly complex bug: PR18773.

The crux of the issue is that LCSSA doesn't preserve stateful alias
analyses. Before r200067, LICM didn't cause LCSSA to run in the LTO pass
manager, where LICM runs essentially without any of the other loop
passes. As a consequence the globalmodref-aa pass run before that loop
pass manager was able to survive the loop pass manager and be used by
DSE to eliminate stores in the function called from the loop body in
Adobe-C++/loop_unroll (and similar patterns in other benchmarks).

When LICM was taught to preserve LCSSA it had to require it as well.
This caused it to be run in the loop pass manager and because it did not
preserve AA, the stateful AA was lost. Most of LLVM's AA isn't stateful
and so this didn't manifest in most cases. Also, in most cases LCSSA was
already running, and so there was no interesting change.

The real kicker is that LCSSA by its definition (injecting PHI nodes
only) trivially preserves AA! All we need to do is mark it, and then
everything goes back to working as intended. It probably was blocking
some other weird cases of stateful AA but the only one I have is
a 1000-line IR test case from loop_unroll, so I don't really have a good
test case here.

Hopefully this fixes the regressions on performance that have been seen
since that revision.

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5 years agoMerging r198863:
Tom Stellard [Tue, 8 Apr 2014 21:18:07 +0000 (21:18 +0000)]
Merging r198863:

------------------------------------------------------------------------
r198863 | stpworld | 2014-01-09 07:26:12 -0500 (Thu, 09 Jan 2014) | 6 lines

Fixed old typo in ScalarEvolution, that caused wrong SCEVs zext operation.
Detailed description is here:
http://llvm.org/bugs/show_bug.cgi?id=18000#c16

For participation in bugfix process special thanks to David Wiberg.

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5 years agoMerging r198744:
Tom Stellard [Tue, 8 Apr 2014 14:28:03 +0000 (14:28 +0000)]
Merging r198744:

------------------------------------------------------------------------
r198744 | iain | 2014-01-08 05:22:54 -0500 (Wed, 08 Jan 2014) | 8 lines

[patch] Adjust behavior of FDE cross-section relocs for targets that don't support abs-differences.

Modern versions of OSX/Darwin's ld (ld64 > 97.17) have an optimisation present that allows the back end to omit relocations (and replace them with an absolute difference) for FDE some text section refs.

This patch allows a backend to opt-in to this behaviour by setting "DwarfFDESymbolsUseAbsDiff".  At present, this is only enabled for modern x86 OSX ports.

test changes by David Fang.

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5 years agoMerging r197574:
Tom Stellard [Tue, 8 Apr 2014 14:27:58 +0000 (14:27 +0000)]
Merging r197574:

------------------------------------------------------------------------
r197574 | rafael.espindola | 2013-12-18 10:06:25 -0500 (Wed, 18 Dec 2013) | 8 lines

Fix f64 and f128 for ppc-darwin.

This patch adds -f64:32:64 to 32 bit ppc darwin since a f64 inside a
structure are only 32 bit aligned.

The patch also drop -f128:64:128 from all ppc darwin, since f128 is
128 bit aligned.

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5 years agoMerging r197572:
Tom Stellard [Tue, 8 Apr 2014 14:27:55 +0000 (14:27 +0000)]
Merging r197572:

------------------------------------------------------------------------
r197572 | rafael.espindola | 2013-12-18 09:35:37 -0500 (Wed, 18 Dec 2013) | 6 lines

One ppc32-darwin, a i64 inside a structure can have 32 bit alignment.

Thanks for Iain Sandoe for testing this with the original gcc.

Clang was already getting this right.

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5 years agoMerging r196987:
Tom Stellard [Tue, 8 Apr 2014 14:27:52 +0000 (14:27 +0000)]
Merging r196987:

------------------------------------------------------------------------
r196987 | rafael.espindola | 2013-12-10 19:09:06 -0500 (Tue, 10 Dec 2013) | 2 lines

Move PPC's getDataLayoutString out of line and document it better.

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5 years agoMerging r196168:
Tom Stellard [Tue, 8 Apr 2014 14:27:47 +0000 (14:27 +0000)]
Merging r196168:

------------------------------------------------------------------------
r196168 | rafael.espindola | 2013-12-02 18:04:51 -0500 (Mon, 02 Dec 2013) | 2 lines

Convert two char* that are only ever used as booleans to bool.

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5 years agoMerging r203818:
Tom Stellard [Mon, 24 Mar 2014 18:21:44 +0000 (18:21 +0000)]
Merging r203818:

------------------------------------------------------------------------
r203818 | thomas.stellard | 2014-03-13 10:13:04 -0700 (Thu, 13 Mar 2014) | 7 lines

R600: LDS instructions shouldn't implicitly define OQAP

LDS instructions are pseudo instructions which model
the OQAP defs and uses within a single instruction.

This fixes a hang in the opencv MedianFilter tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204650 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r203281:
Tom Stellard [Mon, 24 Mar 2014 18:21:43 +0000 (18:21 +0000)]
Merging r203281:

------------------------------------------------------------------------
r203281 | thomas.stellard | 2014-03-07 12:12:39 -0800 (Fri, 07 Mar 2014) | 4 lines

R600/SI: Using SGPRs is illegal for instructions that read carry-out
from VCC

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204649 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r201097:
Tom Stellard [Mon, 24 Mar 2014 18:21:41 +0000 (18:21 +0000)]
Merging r201097:

------------------------------------------------------------------------
r201097 | thomas.stellard | 2014-02-10 08:58:30 -0800 (Mon, 10 Feb 2014) | 9 lines

R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are
used

DS instructions that access local memory can only uses addresses that
are less than or equal to the value of M0.  When M0 is uninitialized,
then we experience undefined behavior.

This patch also changes the behavior to emit S_WQM_B64 on pixel shaders
no matter what kind of DS instruction is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204648 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r201096:
Tom Stellard [Mon, 24 Mar 2014 18:21:40 +0000 (18:21 +0000)]
Merging r201096:

------------------------------------------------------------------------
r201096 | thomas.stellard | 2014-02-10 08:58:27 -0800 (Mon, 10 Feb 2014) | 6 lines

R600/SI: Only use S_WQM_B64 in pixel shaders

This doesn't change any functionality, since we only have two shader
types (compute and pixel) that use local memory.  We're just changing
the logic to match the documentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204647 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r200830:
Tom Stellard [Mon, 24 Mar 2014 18:21:38 +0000 (18:21 +0000)]
Merging r200830:

------------------------------------------------------------------------
r200830 | michel.daenzer | 2014-02-05 01:48:05 -0800 (Wed, 05 Feb 2014) | 8 lines

R600/SI: Add pattern for zero-extending i1 to i32

Fixes opencl-example if_* tests with radeonsi.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74469

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204646 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r200776:
Tom Stellard [Mon, 24 Mar 2014 18:21:37 +0000 (18:21 +0000)]
Merging r200776:

------------------------------------------------------------------------
r200776 | thomas.stellard | 2014-02-04 09:18:43 -0800 (Tue, 04 Feb 2014) | 9 lines

R600/SI: Expand i1 BR_CC

This fixes a crashes in the OpenCV test suite and also the scrypt
kernel in bfgminer.

I was unable to come up with a reduced test case for this.

https://bugs.freedesktop.org/show_bug.cgi?id=72785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204645 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r200775:
Tom Stellard [Mon, 24 Mar 2014 18:21:35 +0000 (18:21 +0000)]
Merging r200775:

------------------------------------------------------------------------
r200775 | thomas.stellard | 2014-02-04 09:18:42 -0800 (Tue, 04 Feb 2014) | 5 lines

R600/SI: Don't assume copies will be coalesced in SIFixSGPRCopies

There is no lit test for this, because it would be too big and
complicated, but it does fix a crash in the Arithm/Absdiff.* OpenCV
test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204644 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r200743:
Tom Stellard [Mon, 24 Mar 2014 18:21:34 +0000 (18:21 +0000)]
Merging r200743:

------------------------------------------------------------------------
r200743 | michel.daenzer | 2014-02-03 23:12:38 -0800 (Mon, 03 Feb 2014) | 11 lines

R600/SI: Fix fneg for 0.0

V_ADD_F32 with source modifier does not produce -0.0 for this. Just
manipulate the sign bit directly instead.

Also add a pattern for (fneg (fabs ...)).

Fixes a bunch of bit encoding piglit tests with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204643 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r200283:
Tom Stellard [Mon, 24 Mar 2014 18:21:32 +0000 (18:21 +0000)]
Merging r200283:

------------------------------------------------------------------------
r200283 | michel.daenzer | 2014-01-27 19:01:16 -0800 (Mon, 27 Jan 2014) | 6 lines

R600/SI: Add pattern for truncating i32 to i1

Fixes half a dozen piglit tests with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204642 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r199919:
Tom Stellard [Mon, 24 Mar 2014 18:21:30 +0000 (18:21 +0000)]
Merging r199919:

------------------------------------------------------------------------
r199919 | thomas.stellard | 2014-01-23 10:49:34 -0800 (Thu, 23 Jan 2014) | 10 lines

R600: Remove successive JUMP in AnalyzeBranch when AllowModify is true

This fixes a crash in the OpenCV OpenCL test suite.

There is no lit test for this, because the test would be very large
and could easily be invalidated by changes to the scheduler
or other parts of the compiler.

Patch by:  Vincent Lejeune

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204641 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r199918:
Tom Stellard [Mon, 24 Mar 2014 18:21:29 +0000 (18:21 +0000)]
Merging r199918:

------------------------------------------------------------------------
r199918 | thomas.stellard | 2014-01-23 10:49:33 -0800 (Thu, 23 Jan 2014) | 8 lines

R600: Disable the BFE pattern

This pattern uses an SDNodeXForm, which isn't being emitted for some
reason.  I can get it to work by attaching the PatLeaf that has the
XForm to the argument in the output pattern, but this results in an
immediate being used in a register operand, which the backend can't
handle yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204640 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r199917:
Tom Stellard [Mon, 24 Mar 2014 18:21:27 +0000 (18:21 +0000)]
Merging r199917:

------------------------------------------------------------------------
r199917 | thomas.stellard | 2014-01-23 10:49:31 -0800 (Thu, 23 Jan 2014) | 6 lines

R600: Correctly handle vertex fetch clauses the precede ENDIFs

The control flow finalizer would sometimes use an ALU_POP_AFTER
instruction before the vetex fetch clause instead of using a POP
instruction after it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204639 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r202336:
Tom Stellard [Mon, 24 Mar 2014 18:21:25 +0000 (18:21 +0000)]
Merging r202336:

------------------------------------------------------------------------
r202336 | michel.daenzer | 2014-02-26 17:47:02 -0800 (Wed, 26 Feb 2014) | 4 lines

R600/SI: Allow SI_KILL for geometry shaders

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204638 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r200196:
Tom Stellard [Mon, 24 Mar 2014 18:21:23 +0000 (18:21 +0000)]
Merging r200196:

------------------------------------------------------------------------
r200196 | michel.daenzer | 2014-01-26 23:20:51 -0800 (Sun, 26 Jan 2014) | 4 lines

R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204637 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r200195:
Tom Stellard [Mon, 24 Mar 2014 18:21:21 +0000 (18:21 +0000)]
Merging r200195:

------------------------------------------------------------------------
r200195 | michel.daenzer | 2014-01-26 23:20:44 -0800 (Sun, 26 Jan 2014) | 4 lines

R600/SI: Add intrinsic for S_SENDMSG instruction

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204636 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoBump version to 3.4.1
Tom Stellard [Wed, 19 Mar 2014 21:40:45 +0000 (21:40 +0000)]
Bump version to 3.4.1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204266 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r202720:
Tom Stellard [Wed, 19 Mar 2014 20:36:02 +0000 (20:36 +0000)]
Merging r202720:

------------------------------------------------------------------------
r202720 | thomas.stellard | 2014-03-03 07:22:00 -0800 (Mon, 03 Mar 2014) | 8 lines

Add patch level to llvm version in CMake and Autoconf

The shared library generated by autoconf will now be called
libLLVM-$(VERSION_MAJOR).$(VERSION_MINOR).$(VERSION_PATCH)$(VERSION_SUFFIX).so
and a symlink named
libLLVM-$(VERSION_MAJOR).$(VERSION_MINOR)$(VERSION_SUFFIX).so will
also be created in the install directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204262 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197503, r197505, r197520:
Tom Stellard [Mon, 24 Feb 2014 18:47:58 +0000 (18:47 +0000)]
Merging r197503, r197505, r197520:

------------------------------------------------------------------------
r197520 | dexonsmith | 2013-12-17 12:28:21 -0800 (Tue, 17 Dec 2013) | 7
lines

Assert that the last operand is actually EFLAGS

This is another follow-up to r197503, after a post-commit review by
Andy.

<rdar://problem/15627766>

------------------------------------------------------------------------
r197505 | dexonsmith | 2013-12-17 08:20:37 -0800 (Tue, 17 Dec 2013) | 6
lines

Setting the CPU in the new vaargs test

Trying to fix buildbots after r197503 (test passes locally).

<rdar://problem/15627766>

------------------------------------------------------------------------
r197503 | dexonsmith | 2013-12-17 07:54:45 -0800 (Tue, 17 Dec 2013) | 17
lines

Revert "Revert "Mark vastart_save_xmm_regs as changing EFLAGS""

This reverts commit r197481, recommiting r197469 with an extra fix.

The vastart_save_xmm_regs pseudo-instruction expands to a test and a
branch, so it modifies EFLAGS.  Mark it so, or else the scheduler might
place it in the middle of another test+branch.

This fixes a bug exposed by r192750, which changed the initial scheduler
to source-order as part of enabling the MI Scheduler for X86.

This re-commit changes the VASTART_SAVE_XMM_REGS custom inserter not to
try to save %flags, and adds a test that catches the bad behavior of
r197469.

<rdar://problem/15627766>

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@202060 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197483:
Bill Wendling [Tue, 24 Dec 2013 06:50:45 +0000 (06:50 +0000)]
Merging r197483:
------------------------------------------------------------------------
r197483 | yrnkrn | 2013-12-17 00:40:11 -0800 (Tue, 17 Dec 2013) | 8 lines

There are no __register_frame and __deregister_frame functions
when using structured exception handling (SEH) on Windows 64.

http://llvm-reviews.chandlerc.com/D2378

Patch by Jonathan Liu!

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197944 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoSmall reformatting changes.
Bill Wendling [Tue, 24 Dec 2013 06:29:42 +0000 (06:29 +0000)]
Small reformatting changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197932 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoRemove help notes from the ReleaseNotes.
Bill Wendling [Fri, 20 Dec 2013 22:14:38 +0000 (22:14 +0000)]
Remove help notes from the ReleaseNotes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197840 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197492:
Bill Wendling [Fri, 20 Dec 2013 04:29:56 +0000 (04:29 +0000)]
Merging r197492:
------------------------------------------------------------------------
r197492 | dyatkovskiy | 2013-12-17 04:07:33 -0800 (Tue, 17 Dec 2013) | 26 lines

Fix for PR18045:
http://llvm.org/bugs/show_bug.cgi?id=18045

Short issue description:
For X86 machines with sse < sse4.1 we got failures for some
particular load/store vector sequences:

$ clang-trunk -m32 -O2 test-case.c
fatal error: error in backend: Cannot select: 0x4200920: v4i32,ch = load 0x41d6ab0, 0x4205850,
      0x41dcb10<LD16[getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)](align=4)> [ORD=82]
      [ID=58]
  0x4205850: i32 = X86ISD::Wrapper 0x41d5490 [ORD=26] [ID=43]
    0x41d5490: i32 = TargetGlobalAddress<[4 x i32]* @e> 0 [ORD=26] [ID=23]
  0x41dcb10: i32 = undef [ID=2]

The reason is that EltsFromConsecutiveLoads could emit such load instruction
both before and after legalize stage. Though this instruction is not legal for
machines with SSSE3 and lower.

The fix: In EltsFromConsecutiveLoads, if we have passed legalize stage, we
check whether nodes it emits are legal.

P.S.: If you get failure in time from 12:00 and till 22:00 (UTC-8),
perhaps I'll slow with response, so you better reject this commit. Thanks!

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197779 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197718:
Bill Wendling [Fri, 20 Dec 2013 04:26:57 +0000 (04:26 +0000)]
Merging r197718:
------------------------------------------------------------------------
r197718 | hans | 2013-12-19 12:32:44 -0800 (Thu, 19 Dec 2013) | 10 lines

Make sys::ThreadLocal<> zero-initialized on non-thread builds (PR18205)

According to the docs, ThreadLocal<>::get() should return NULL
if no object has been set. This patch makes that the case also for non-thread
builds and adds a very basic unit test to check it.

(This was causing PR18205 because PrettyStackTraceHead didn't get zero-
initialized and we'd crash trying to read past the end of that list. We didn't
notice this so much on Linux since we'd crash after printing all the entries,
but on Mac we print into a SmallString, and would crash before printing that.)
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197778 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoUpdate notes.
Bill Wendling [Tue, 17 Dec 2013 06:01:39 +0000 (06:01 +0000)]
Update notes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197468 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197449:
Bill Wendling [Tue, 17 Dec 2013 01:28:35 +0000 (01:28 +0000)]
Merging r197449:
------------------------------------------------------------------------
r197449 | arnolds | 2013-12-16 17:11:01 -0800 (Mon, 16 Dec 2013) | 7 lines

LoopVectorizer: Don't if-convert constant expressions that can trap

A phi node operand or an instruction operand could be a constant expression that
can trap (division). Check that we don't vectorize such cases.

PR16729
radar://15653590
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197453 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r195411:
Bill Wendling [Mon, 16 Dec 2013 03:48:58 +0000 (03:48 +0000)]
Merging r195411:
------------------------------------------------------------------------
r195411 | mgottesman | 2013-11-21 21:00:51 -0800 (Thu, 21 Nov 2013) | 1 line

[block-freq] Update data in test case to be unsigned long long to fix mingw build.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197363 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197047:
Bill Wendling [Sun, 15 Dec 2013 21:02:34 +0000 (21:02 +0000)]
Merging r197047:
------------------------------------------------------------------------
r197047 | d0k | 2013-12-11 08:36:09 -0800 (Wed, 11 Dec 2013) | 3 lines

SelectionDAG: Fix a typo.

Found by "cppcheck". PR18208.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197355 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r195710:
Bill Wendling [Sun, 15 Dec 2013 20:58:02 +0000 (20:58 +0000)]
Merging r195710:
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197354 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197216:
Bill Wendling [Sun, 15 Dec 2013 20:55:09 +0000 (20:55 +0000)]
Merging r197216:
------------------------------------------------------------------------
r197216 | chandlerc | 2013-12-13 00:00:01 -0800 (Fri, 13 Dec 2013) | 9 lines

[inliner] Fix PR18206 by preventing inlining functions that call setjmp
through an invoke instruction.

The original patch for this was written by Mark Seaborn, but I've
reworked his test case into the existing returns_twice test case and
implemented the fix by the prior refactoring to actually run the cost
analysis over invoke instructions, and then here fixing our detection of
the returns_twice attribute to work for both calls and invokes. We never
noticed because we never saw an invoke. =[
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197352 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197215:
Bill Wendling [Sun, 15 Dec 2013 20:54:53 +0000 (20:54 +0000)]
Merging r197215:
------------------------------------------------------------------------
r197215 | chandlerc | 2013-12-12 23:59:56 -0800 (Thu, 12 Dec 2013) | 24 lines

[inliner] Completely change (and fix) how the inline cost analysis
handles terminator instructions.

The inline cost analysis inheritted some pretty rough handling of
terminator insts from the original cost analysis, and then made it much,
much worse by factoring all of the important analyses into a separate
instruction visitor. That instruction visitor never visited the
terminator.

This works fine for things like conditional branches, but for many other
things we simply computed The Wrong Value. First example are
unconditional branches, which should be free but were counted as full
cost. This is most significant for conditional branches where the
condition simplifies and folds during inlining. We paid a 1 instruction
tax on every branch in a straight line specialized path. =[

Oh, we also claimed that the unreachable instruction had cost.

But it gets worse. Let's consider invoke. We never applied the call
penalty. We never accounted for the cost of the arguments. Nope. Worse
still, we didn't handle the *correctness* constraints of not inlining
recursive invokes, or exception throwing returns_twice functions. Oops.
See PR18206. Sadly, PR18206 requires yet another fix, but this
refactoring is at least a huge step in that direction.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197351 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAdd release notes for the PowerPC backend
Hal Finkel [Sat, 14 Dec 2013 14:41:55 +0000 (14:41 +0000)]
Add release notes for the PowerPC backend

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197325 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197178:
Bill Wendling [Sat, 14 Dec 2013 08:04:09 +0000 (08:04 +0000)]
Merging r197178:
------------------------------------------------------------------------
r197178 | hfinkel | 2013-12-12 12:45:24 -0800 (Thu, 12 Dec 2013) | 9 lines

Fix a use-after-free error in GlobalOpt CleanupConstantGlobalUsers

GlobalOpt's CleanupConstantGlobalUsers function uses a worklist array to manage
constant users to be visited. The pointers in this array need to be weak
handles because when we delete a constant array, we may also be holding a
pointer to one of its elements (or an element of one of its elements if we're
dealing with an array of arrays) in the worklist.

Fixes PR17347.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197322 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197228:
Bill Wendling [Sat, 14 Dec 2013 08:01:30 +0000 (08:01 +0000)]
Merging r197228:
------------------------------------------------------------------------
r197228 | d0k | 2013-12-13 05:40:24 -0800 (Fri, 13 Dec 2013) | 8 lines

X86: When lowering shl_parts, don't emit shift amounts larger than the bit width.

While it's safe for the X86-specific shift nodes, dag combining will
kill generic nodes. Insert an AND to make it safe, isel will nuke it
as x86's shift instructions have an implicit AND.

Fixes PR16108, which contains a contraption to hit this case in between
constant folders.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197321 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoFix URL.
Bill Wendling [Fri, 13 Dec 2013 04:19:05 +0000 (04:19 +0000)]
Fix URL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197203 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r-197100:
Bill Wendling [Thu, 12 Dec 2013 06:44:57 +0000 (06:44 +0000)]
Merging r-197100:
------------------------------------------------------------------------
r197100 | hfinkel | 2013-12-11 16:23:29 -0800 (Wed, 11 Dec 2013) | 1 line

Remove unused multiclass from PPCInstrInfo.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197131 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197100:
Bill Wendling [Thu, 12 Dec 2013 06:42:41 +0000 (06:42 +0000)]
Merging r197100:
------------------------------------------------------------------------
r197100 | hfinkel | 2013-12-11 16:23:29 -0800 (Wed, 11 Dec 2013) | 1 line

Remove unused multiclass from PPCInstrInfo.td
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197130 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r197089:
Bill Wendling [Thu, 12 Dec 2013 04:28:52 +0000 (04:28 +0000)]
Merging r197089:
------------------------------------------------------------------------
r197089 | hfinkel | 2013-12-11 15:12:25 -0800 (Wed, 11 Dec 2013) | 6 lines

Fix the PPC subsumes-predicate check

For one predicate to subsume another, they must both check the same condition
register. Failure to check this prerequisite was causing miscompiles.

Fixes PR18003.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197126 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoAdd LibBeauty blurb.
Bill Wendling [Wed, 11 Dec 2013 04:18:46 +0000 (04:18 +0000)]
Add LibBeauty blurb.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197004 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r196768:
Bill Wendling [Tue, 10 Dec 2013 18:46:12 +0000 (18:46 +0000)]
Merging r196768:
------------------------------------------------------------------------
r196768 | majnemer | 2013-12-09 01:04:00 -0800 (Mon, 09 Dec 2013) | 5 lines

ADT: Implement MutableArrayRef::reverse_iterator

This adds rbegin/rend methods to MutableArrayRef, they will be used by a
follow-on commit in clang.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196945 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r196858:
Bill Wendling [Tue, 10 Dec 2013 06:42:24 +0000 (06:42 +0000)]
Merging r196858:
------------------------------------------------------------------------
r196858 | nadav | 2013-12-09 17:13:59 -0800 (Mon, 09 Dec 2013) | 1 line

Fix PR18162 - Incorrect assertion assumed that the SDValue resno is zero.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196886 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r196806:
Bill Wendling [Tue, 10 Dec 2013 04:31:42 +0000 (04:31 +0000)]
Merging r196806:
------------------------------------------------------------------------
r196806 | apazos | 2013-12-09 11:29:14 -0800 (Mon, 09 Dec 2013) | 11 lines

Fix pattern match for movi with 0D result

Patch by Jiangning Liu.

With some test case changes:
- intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll.
- New test cases to cover movi 1D scenario without using the intrinsic in
test/CodeGen/AArch64/neon-mov.ll.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196872 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r196612:
Bill Wendling [Tue, 10 Dec 2013 04:29:40 +0000 (04:29 +0000)]
Merging r196612:
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196869 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r196172:
Manman Ren [Mon, 9 Dec 2013 21:07:27 +0000 (21:07 +0000)]
Merging r196172:
------------------------------------------------------------------------
r196172 | mren | 2013-12-02 16:12:14 -0800 (Mon, 02 Dec 2013) | 4 lines

Debug Info: rename getDebugInfoVersionFromModule to getDebugMetadataVersionFromModule.

Suggested by Eric.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196823 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r196158:
Manman Ren [Mon, 9 Dec 2013 21:06:30 +0000 (21:06 +0000)]
Merging r196158:
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r196158 | mren | 2013-12-02 13:29:56 -0800 (Mon, 02 Dec 2013) | 12 lines

Debug Info: drop debug info via upgrading path if version number does not match.

Add a helper function getDebugInfoVersionFromModule to return the debug info
version number for a module.

"Verifier/module-flags-1.ll" checks for verification errors.
It will seg fault when calling getDebugInfoVersionFromModule because of the
incorrect format for module flags in the testing case. We make
getModuleFlagsMetadata more robust by checking for error conditions.

PR17982

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196822 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r196156:
Manman Ren [Mon, 9 Dec 2013 21:05:36 +0000 (21:05 +0000)]
Merging r196156:
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r196156 | mren | 2013-12-02 13:25:56 -0800 (Mon, 02 Dec 2013) | 2 lines

Update Ocaml/vmcore.ml to emit a "Debug Info Version" module flag.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196821 91177308-0d34-0410-b5e6-96231b3b80d8

5 years agoMerging r196144:
Manman Ren [Mon, 9 Dec 2013 21:03:35 +0000 (21:03 +0000)]
Merging r196144:
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r196144 | mren | 2013-12-02 12:09:52 -0800 (Mon, 02 Dec 2013) | 4 lines

Debug Info: Move the constant for Debug Info Version from Dwarf.h to Metadata.h.

Suggested by Eric.

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5 years agoMerging r195535:
Manman Ren [Mon, 9 Dec 2013 21:01:06 +0000 (21:01 +0000)]
Merging r195535:
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r195535 | mren | 2013-11-22 17:16:29 -0800 (Fri, 22 Nov 2013) | 8 lines

Debug Info: update testing cases to specify the debug info version number.

We are going to drop debug info without a version number or with a different
version number, to make sure we don't crash when we see bitcode files with
different debug info metadata format.

Make tests more robust by removing hard-coded metadata numbers in CHECK lines.

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5 years agoMerging r195505:
Manman Ren [Mon, 9 Dec 2013 21:00:02 +0000 (21:00 +0000)]
Merging r195505:
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r195505 | mren | 2013-11-22 14:06:31 -0800 (Fri, 22 Nov 2013) | 8 lines

Debug Info: move StripDebugInfo from StripSymbols.cpp to DebugInfo.cpp.

We can share the implementation between StripSymbols and dropping debug info
for metadata versions that do not match.

Also update the comments to match the implementation. A follow-on patch will
drop the "Debug Info Version" module flag in StripDebugInfo.

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5 years agoMerging r195504:
Manman Ren [Mon, 9 Dec 2013 20:58:24 +0000 (20:58 +0000)]
Merging r195504:
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r195504 | mren | 2013-11-22 13:49:45 -0800 (Fri, 22 Nov 2013) | 6 lines

Debug Info: update testing cases to specify the debug info version number.

We are going to drop debug info without a version number or with a different
version number, to make sure we don't crash when we see bitcode files with
different debug info metadata format.

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5 years agoMerge rest of r196210. Some bits strayed into r196701, turning 3.4 red. This
Tim Northover [Mon, 9 Dec 2013 10:48:32 +0000 (10:48 +0000)]
Merge rest of r196210. Some bits strayed into r196701, turning 3.4 red. This
should fix the issue.
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r196210 | haoliu | 2013-12-03 06:06:55 +0000 (Tue, 03 Dec 2013) | 3 lines

[AArch64]Add missing floating point convert, round and misc intrinsics.
E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn

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5 years agoMerge r196725 (conflicts on same API as before):
Tim Northover [Mon, 9 Dec 2013 09:05:30 +0000 (09:05 +0000)]
Merge r196725 (conflicts on same API as before):
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r196725 | tnorthover | 2013-12-08 15:56:50 +0000 (Sun, 08 Dec 2013) |
19 lines

ARM: fix folding of stack-adjustment (yet again).

When trying to eliminate an "sub sp, sp, #N" instruction by folding
it into an existing push/pop using dummy registers, we need to account
for the fact that this might affect precisely how "fp" gets set in the
prologue.

We were attempting this, but assuming that *whenever* we performed a
fold it would make a difference. This is false, for example, in:
    push {r4, r7, lr}
    add fp, sp, #4
    vpush {d8}
    sub sp, sp, #8

we can fold the "sub" into the "vpush", forming "vpush {d7, d8}".
However, in that case the "add fp" instruction mustn't change, which
we were getting wrong before.

Should fix PR18160.
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5 years agoMerging r196751:
Bill Wendling [Mon, 9 Dec 2013 08:56:18 +0000 (08:56 +0000)]
Merging r196751:
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r196751 | venkatra | 2013-12-08 20:02:15 -0800 (Sun, 08 Dec 2013) | 3 lines

[Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error.

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5 years agoMerging r196755:
Bill Wendling [Mon, 9 Dec 2013 08:55:55 +0000 (08:55 +0000)]
Merging r196755:
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r196755 | venkatra | 2013-12-08 21:13:25 -0800 (Sun, 08 Dec 2013) | 2 lines

[SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9.

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